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report [2013/06/13 00:32] – [Motivation] team2 | report [2013/06/14 16:45] (current) – [Architecture and design] team2 | ||
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Since there is only one I2C bus available in the analog pins 4 (Serial Data Line) and 5 (Serial Clock), and both the accelerometer and the EEPROM need to access it, it was necessary to adapt and control the bus access. To avoid including more hardware to the device, i.e. an I2C multiplexer, | Since there is only one I2C bus available in the analog pins 4 (Serial Data Line) and 5 (Serial Clock), and both the accelerometer and the EEPROM need to access it, it was necessary to adapt and control the bus access. To avoid including more hardware to the device, i.e. an I2C multiplexer, | ||
- | {{:power_schematic.jpg?300|}} | + | {{:power_schematicchanged.jpg?300|}} |
//Figure 28 - Power schematic// | //Figure 28 - Power schematic// |